China’s domestic semiconductor industry landscape has changed considerably. The Biden administration has continued to impose export control restrictions on Chinese firms, and the October 7, 2022, package of controls targeted not only advanced semiconductors (such as GPUs used for running artificial intelligence and machine learning workloads) but also expanded significantly on controls over semiconductor manufacturing equipment (SME). One goal of the U.S. controls is to prevent Chinese firms from moving into nonplanar technology processes, such as FinFET and eventually Gate All Around (GAA). The new restrictions included novel end-use controls and controls on U.S. persons, posing major new challenges...
Nope. China won’t figured it out and will only be able to do semiconductors that trail behind a lot for a very long time.
The smallest node that actually works for them is 16 nm, SMIC’s 7 nm in the new Kirin 9000S Chip is not even close, especially compared to the Krin 9000 wich is made with TSMCs 5nm node. Performance and Efficiency are up to 45% behind TSMCs stuff (Which is not something that can be explained away with just because of the smaller node).
But that’s not all: The way SMIC manufactures these chips is extremely expensive, due to the fact that they have to use multi-patterning. This also effects yields significant. They have no chance to compete on the open market against Samsung, Intel and TSMC, even with the high subsidies from the Chinese government. Also, while the way they are being produced allows for 6 nm, the gate length and contact width are going to reduce yield even more.
7nm isn’t close to 5nm? There’s a difference of 45%? What! No way!
Fact is, the Huawei Mate 60 has moved over 30 million units. While that’s in no way comparable to Apple’s 200+ million units annually, it’s a significant scale representing a robust supply chain that’s capable of churning out functioning chips. If, by your claims, yields are low because of an immature process, then you’d only expect yields to go up as the process matures.
Yield is not a static factor, but one built on by process development and co-design. You can look at how Intel’s yields have increased over the years: they refrained from using EUV on their 10nm (Intel 7) process and, while they ran into a bunch of engineering challenges and delays, still ended up shipping Intel 7 at scale.
These aren’t unsolvable issues, but ones of engineering and manpower and skill. EUV still requires multi-patterning for 3nm, so it’s not like the problem has been eliminated.
Nope. China won’t figured it out and will only be able to do semiconductors that trail behind a lot for a very long time. The smallest node that actually works for them is 16 nm, SMIC’s 7 nm in the new Kirin 9000S Chip is not even close, especially compared to the Krin 9000 wich is made with TSMCs 5nm node. Performance and Efficiency are up to 45% behind TSMCs stuff (Which is not something that can be explained away with just because of the smaller node).
But that’s not all: The way SMIC manufactures these chips is extremely expensive, due to the fact that they have to use multi-patterning. This also effects yields significant. They have no chance to compete on the open market against Samsung, Intel and TSMC, even with the high subsidies from the Chinese government. Also, while the way they are being produced allows for 6 nm, the gate length and contact width are going to reduce yield even more.
So they simply can’t flood the market.
7nm isn’t close to 5nm? There’s a difference of 45%? What! No way!
Fact is, the Huawei Mate 60 has moved over 30 million units. While that’s in no way comparable to Apple’s 200+ million units annually, it’s a significant scale representing a robust supply chain that’s capable of churning out functioning chips. If, by your claims, yields are low because of an immature process, then you’d only expect yields to go up as the process matures.
Yield is not a static factor, but one built on by process development and co-design. You can look at how Intel’s yields have increased over the years: they refrained from using EUV on their 10nm (Intel 7) process and, while they ran into a bunch of engineering challenges and delays, still ended up shipping Intel 7 at scale.
These aren’t unsolvable issues, but ones of engineering and manpower and skill. EUV still requires multi-patterning for 3nm, so it’s not like the problem has been eliminated.